1. Field of the Invention
The present invention relates to a display appliance, and more particularly, to an apparatus and method for outputting digital video data in a display appliance.
2. Description of the Related Art
Referring to FIG. 1 showing a block diagram of a conventional apparatus for receiving/transmitting digital video data, a transmitter 100 includes a video processor 102 and a D/A converter 104, and a receiver 106 includes an A/D converter 108 and a video processor 110.
The digital video data outputted from the video processor 102 of the transmitter 100 is converted into an analog video signal by the D/A converter 104. The analog video signal is transmitted to the receiver 106 via a D-sub cable or the like. The A/D converter of the receiver 106 converts the analog video signal received via the D-sub cable into the digital video data.
The digital video data is inputted to the digital video processor 110. The video processor 110 converts and outputs the digital video data which is suitable to be displayed. The analog video signal transmitted through the D-sub cable consists of R, G, B, and horizontal and vertical sync signals.
With the construction as described above, the digital video data is converted into the analog video signal and then the analog video signal is converted into the digital video data, which causes damage to the digital video data.
In order to solve the above problem, DDWG (Digital Display Working Group) addresses the requirement for a digital interface system transmitting the digital video data in a digital mode. According to DVI (Digital Visual Interface), which is a digital interface system, developed by the DDWG, a transmitting side encodes an input data and various control signals to transmit them via a dedicated connector, while a receiving side decodes the encoded data. The DVI includes TMDS (Transition Minimized Differential Signaling), LVDS (Low Voltage Differential Signaling), GVIF (Gigabit Video Interface) or the like.
Referring to FIG. 2 showing a block diagram of a transmitter/receiver of TMDS, data inputted to a transmitter 200 includes first digital video data B, second digital video data G, third digital video data R, horizontal and vertical sync signals, first to fourth control data, DE and a clock. A first encoder 202 of the transmitter 200 receives and encodes the first digital video data B, the horizontal and vertical sync signals and the DE, and converts them into serial data to transmit them via a first channel of a TMDS link. A second encoder 204 of the transmitter 200 receives and encodes the second digital video data G, the first and second control data and DE, and converts them into serial data to transmit them via a second channel of the TMDS link. Further, a third encoder 206 of the transmitter 200 receives and encodes the third digital video data R, the third and fourth control data and DE, and converts them into serial data to transmit them via a third channel of the TMDS link. The clock is transmitted via a fourth channel of the TMDS link as is.
A first encoder 210 of the receiver 208 receives the signals inputted via the first channel of the TMDS link, converts the signals into parallel data, and decodes the signals to output the first digital video data B, the horizontal and vertical sync signals and the DE0. A second decoder 212 receives the signals inputted via the second channel of the TMDS link, coverts the signals into parallel data, and decodes the signals to output the second digital video data G, the first and second control data and DE1. A third decoder 214 receives the signals inputted via the third channel of the TMDS link, converts the signals into parallel data, and decodes the signals to output the third digital video data R, the third and fourth control data and DE2.
The output data of the first to third decoders 210 to 214 and the clock received via the fourth channel of the TMDS link are inputted to an inter-channel arranging unit 216. The inter-channel arranging unit 216 arranges various inputted data and the clock to output them in the same format as the inputted format.
The DVI connector includes a DVI-D connector capable of transmitting/receiving only the digital video data, and a DVI-I connector capable of transmitting/receiving the digital video data and the analog video signal.
Referring to FIG. 3 showing a view of the pin arrangement of the DVI-D connector, the DVI-D connector includes 12 pins for transmitting the digital video data, 2 pins for transmitting the clock, and 4 pins for DDC.
Referring to FIG. 4 showing a view of pin arrangement of the DVI-I connector, the DVI-I connector includes 12 pins for transmitting the digital video data, 2 pins for transmitting the clock, 4 pins for DDC, R, G and B pins for transmitting the analog video signal, and pins for transmitting the horizontal and vertical sync signals.
A conventional apparatus for processing the digital video data inputted in the DVI mode in the display appliance will now be described with reference to FIG. 5.
The digital video processing apparatus includes a video decoder 300 for receiving and decoding a TV signal to output the decoded signal to a first multiplexer 304, and a component processor 302 for receiving and decoding the DVD signal to output the decoded signal to the first multiplexer 304. The first multiplexer 304 provides a scaler 318 with any one of outputs of the video decoder 300 and a component processor 302 by control of a microprocessor (not shown).
A first A/D converter 306 receives the analog RGB signal and converts analog to digital to output the converted signal to a second multiplexer 316. A second A/D converter 308 receives the analog RGB signal inputted via the DVI connector and converts analog to digital to output the converted signal. A DVI decoder 310 decodes the DVI video data inputted through the DVI connector. The data outputted from the DVI decoder 310 is 8:8:8 RGB digital video data. A signal detecting unit 312 detects whether there is a signal in an analog RGB signal input terminal of the DVI connector and a DVI data input terminal, and generates a selection signal according to the detected results. A switching unit 314 selects any one of outputs of the second 2A/D converter 308 and DVI decoder 310 to output the selected output to the second multiplexer 316. The second multiplexer 316 provides the scaler 318 with any one of outputs of the first A/D converter 306 and switching unit 314 by the control of the microprocessor (not shown).
The scaler 318 scales the digital video data supplied from the first and second multiplexers 304 and 316 to apply the scaled data to the D/A converter 320. The D/A converter 320 converts the digital video data outputted from the scaler 318 into analog video data.
Some display appliances used commonly do not receive TV signal, DVD signal or the like due to spatial or using restrictions.
Therefore, it is required to develop a method for outputting digital video data in a display appliance capable of processing only digital video data.